Increasingly over the past decade, creating smaller and easily portable electronic devices has become a major force driving innovation in product design and technology. This trend has been frustrated to some extent by a coinciding demand for greater functionality, which may require the addition of more components into a device, or growth in the size of existing components to provide additional functions.
Semiconductor (solid state) circuit devices (referred to also as ‘chips’ or ‘die’) are an essential constituent component of most, if not all electronic devices in use today and being designed for the future. In many designs, die are attached to somewhat larger ‘package substrates’ which provide sufficient surface area for ‘breaking out’ the electrical signal from dense interconnect arrays to a number of electrical pathways, or traces, on an even larger substrate. Such package substrates are typically formed as multiple layers of glass fiber, organic resins, copper, and solder mask material. The copper is lithographically or otherwise formed into thin traces at multiple levels of the substrate. Many of the traces then spread outward through the package substrate and connect with vias to provide electrical continuity between electrical interconnects of the die and an array of, for example, solder balls on the opposite side of the substrate from the die. The solder balls provide both physical and electrical attachment to a larger substrate on which other components of the device may reside.
Package substrates, however, present numerous drawbacks detrimental to the objective of designing very small and relatively inexpensive portable electronic devices. For one, the package substrate may be the most expensive part of a package, and this cost goes up as the number of layers in the substrate increases, largely driven by the size and density of a die interconnect array. Further, as the thickness of the package substrate increases, so the overall thickness of the package increases, consuming valuable space in an electronic device, and either constraining or even increasing the minimum size that the device can be designed. Therefore, as mentioned, the complexity of a die to support increased functionality frequently drives a corresponding increase in the size and cost of the package and the overall device.
Further, the longer the electrical pathways are formed to sufficiently break out an interconnect array in a package, the more the electrical performance of the package, and therefore the device, is detrimentally impacted. Thick substrates may also hinder effective thermal dissipation from a device by retaining thermal energy close to the die that should preferably be dissipated away through a passive or active thermal device, such as a heat sink. To counter this, many current designs include a heat spreader attached to the die to more effectively draw heat away from a die. As can be expected, heat spreaders add both cost and size to device packages and electronic devices.
Some manufacturers have taken steps to reduce the size of the cores of package substrates, and coreless substrates have also been proposed. While these approaches do help to reduce the size of package substrates from 1 millimeter or more down to approximately 300 microns in some representative package substrates, they still pose a substantial impediment to further reduction of package size, as well as insufficiently resolving many of the other associated deficiencies described here. Significant challenges remain to further reducing the size and cost of highly functional portable electronic devices to keep pace with the demand for such in the market.